EPROM or EEPROM and methods for making the same are well known in the art. In general, an EPROM or an EEPROM is characterized by a "floating gate" and a electrical connection termed "control gate", both of which are fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline silicon conductive. A typical doping material is phosphorus. The floating gate and the control gate are separated by a layer of insulating material, typically silicon dioxide (SiO.sub.2). The principle upon which the EPROM or EEPROM device operates is that charges are stored on the "floating gate" in a capacitive manner. Thus, the dielectric of the layer of silicon dioxide between the floating gate and the control gate is important.
In the prior art (see for example, U.S. Pat. No. 4,203,158 and W. S. Johnson et al. ISCCC Digest of Technical Papers, pp. 152-153 (February 1980)), the floating gate is formed by reacting SiH.sub.4 in a low pressure chemical vapor deposition chamber and then doped with POCl.sub.3. A layer of silicon dioxide is then deposited, or thermally grown, on the doped polycrystalline layer of silicon. The layer of silicon dioxide is typically approximately 750 Angstroms. Generally, a high oxidation temperature (greater than 1050.degree. C.) and heavier phosphorus doping are required to achieve better interpoly quality on breakdown capability. However, oxidation at high temperature on heavily-doped polysilicon involves several drawbacks, such as: (1) outgassing during interpoly oxidation which causes autodoping on wafer; and (2) oxidation enhanced diffusion of phosphorus from the floating gate to the tunnel oxide, which, forms a trapping center in the oxide. The phosphorus induced trap collapses the threshold window of EEPROM cell at 10.sup.4 cycles. (See: R. B. Marcus et al., J. Electrochem. Soc., p. 1282, June, 1982; K. Saraswat et al., Computer-Aided Design of Integrated Circuit Fabrication Process for VLSI Device, p. 244-290, July, 1981.) Finally, the second layer of doped polycrystalline silicon is then formed on top of the insulating layer of SiO.sub.2.
Because the insulating layer of silicon dioxide is on the order of 750 Angstroms, the typical write or erase voltage, i.e., the voltage which is needed to place charges on or to remove charges off the floating gate has been high, i.e., in excess of 20 volts, which places the shrinkage limits for gate oxide thickness, junction depth and die size.
Silicon nitride (Si.sub.3 N.sub.4) has also been used as an insulating layer of dual dielectric (thermal oxide with silicon nitride on it) between the floating gate and the control gate connection. Silicon nitride has the property that it is more dense than silicon dioxide and, therefore, affords higher capacitive coupling between the floating gate and the control gate. A typical dual dielectric between the floating gate and the control gate is composed of 500 Angstroms oxide and 400 Angstroms nitride. However, even with the use of silicon nitride as the insulating layer, the write and erase voltage is still relatively high, in excess of 20 volts. This is due to the problem of asperity or roughness in the surface of the floating gate. Asperity in the floating gate causes points of electrical field enhancement. Thus, a large amount of insulating material must be interposed between the floating gate and the control gate. This, however, in turn, requires that a large voltage be used. Currently in VLSI technology, there is a preference for small die size in high circuit density packages which requires a relatively high interpoly dielectric breakdown capability and interpoly capacitance.